As the techniques related to the data processing system that the inventors of the present invention have examined, for example, the following techniques are known.
As means for allowing a central processing unit (hereinafter, “CPU”) to execute another task while the CPU is executing a certain instruction (task), a software interrupt and a hardware interrupt are available.
The software interrupt is as follows. If the CPU performs a specific software processing for generating an interrupt (instruction execution), then an interrupt request flag present in an interrupt controller is set on, an interrupt request signal from the interrupt controller to the CPU is asserted (made active (effective)), and the CPU thereby starts executing an interrupt exception handling routine (another task). If the CPU performs a processing for removing the interrupt request (instruction execution) when finishing the execution of the instruction of the interrupt exception handling routine, then the interrupt request flag present in the interrupt controller is cleared, and the interrupt request signal from the interrupt controller to the CPU is negated (made inactive (ineffective)). Then, if the CPU executes a return instruction from the interrupt exception processing, the CPU returns to the instruction execution before the execution of the interrupt exception handling routine.
Examples of the hardware interrupt include a hardware interrupt by an internal peripheral module and a hardware interrupt by an external terminal.
The hardware interrupt by an internal peripheral module is as follows. If some event (e.g., a comparison matching of time module or completion of transmission or reception of a communication module) occurs in an internal peripheral module in the hardware (e.g., a microcontroller), an interrupt request flag present in the corresponding internal peripheral module is set on, an interrupt request signal from the internal peripheral module to the interrupt controller is asserted, and an interrupt request signal from the interrupt controller to the CPU is asserted. The CPU thereby starts executing an interrupt exception handling routine (another task). If the CPU performs a processing for removing the interrupt request (instruction execution) when finishing the execution of the instruction of the interrupt exception handling routine, then the interrupt request flag present in the internal peripheral module is cleared, the interrupt request signal from the internal peripheral module to the interrupt controller is negated, and the interrupt request signal from the interrupt controller to the CPU is negated. Then, if a return instruction from the exception processing is executed, the CPU returns to the instruction execution before the execution of the interrupt exception handling routine.
The hardware interrupt by an external terminal is as follows. If some event (e.g., change in level of an external IRQ terminal) occurs in an external terminal provided in hardware (e.g., a microcontroller), the event is detected and an interrupt request flag present in the interrupt controller is set on. Then, an interrupt request signal from the interrupt controller to the CPU is asserted, and the CPU thereby starts executing the interrupt exception handling routine (another task). If the CPU performs a processing for removing the interrupt request (instruction execution) when finishing the execution of the instruction of the interrupt exception handling routine, the interrupt request flag present in the interrupt controller is cleared and the interrupt request signal from the interrupt controller to the CPU is negated. If a return instruction from the exception processing is executed, the CPU returns to the instruction execution before the execution of the interrupt exception handling routine.
An interrupt processing function is described in, for example, Japanese Patent Application Laid-Open No. 8-314731.
Also, a microcontroller employed for automobile power train control is normally mounted with a floating point unit (hereinafter “FPU”). In the controller of this type, sensor information is converted into digital information by using an analog-digital converter (hereinafter “AD converter”), and a control target is controlled by an arithmetic operation. In the case of analyzing the sensor information changing rapidly, in particular, it is necessary to collect data at a high rate and perform a digital signal processing.
Conventionally, in a method for storing samples used for the digital signal processing such as a knock control, data is transferred from the AD converter to an internal RAM (memory) by using a data transfer processor such as a direct memory access controller (hereinafter, “DMAC”) provided in the microcontroller. After the data is transferred, a transferred data value in the internal RAM is read by the CPU and the digital signal processing is thereby carried out.